The Rough Guide to MBus Modules
Introduction Buses Modules Systems Chips Miscellany

Solbourne Series 6

Solbourne Series 6E

The Series 6 and 6E systems are multi-board server systems using a proprietary KBus backplane. Architecturally, they are similar in philosophy to the Sun SPARCserver-1000 series (but predate it), except that the KBus backplane is circuit-switched not packet-switched like the XDBus.

The Solbourne Series 6 family do not run stock SunOS 4.x or Solaris 2.x - they originally ran a Solbourne-customised version of SunOS 4.x called OS/MP. The Sun Solaris 2.3 CD did include unsupported add-on packages to cater for the Series 6, but I am unaware of anyone successfully running anything other than OS/MP on these systems.

The various models numbers are built from the base chassis-type and the number of CPU boards, eg:

The CPU boards have PGA-socketed SuperSPARC and MXCC chips - 33MHz on the Series 6, 50MHz on the Series 6E. The PGA-socketed MXCC provides access to 1Mb of level-2 cache, backed by a further 16Mb of level-3 cache (needed to protect against high-latency access to memory across the KBus).

The CPU boards also have a single MBus slot. Unfortunately, the board's memory-controller only supports the Level 1 (uniprocessor) MBus protocol, thus the MBus slot can only be used to effectively replace the socketed CPU/MXCC.

The CPU boards have a group of jumper pads (no pins) marked "PLCC Bypass", which presumably would enable the MBus slot at the expense of the socketed CPU/MXCC chips. However, I do not know the exact jumpering arrangement needed to do so. It may also be necessary to physically remove the PGA-socketed CPU and MXCC.

Also, an MBus module is tall enough to require leaving the adjacent KBus backplane slot empty.

Solbourne used the MBus slot to test the CPU boards while TI were having problems producing SuperSPARC chips in sufficient quantities for third-party system manufacturers (a single MBus module could be used to test an essentially unlimited number of boards).

To summarise: CYM6001K, SM100, HyperSPARC and uncached SuperSPARC modules (eg: SM40) are definately not going to work. Cached SuperSPARC modules (eg: SM41, SM51, SM61 in the Series 6, or SM61 in the 6E) should work, but only to replace the extant CPU, and only with a maximum of one module. Even this latter possibility requires additional steps which are unknown to me.

As always, if you have any additional information, please email

Introduction Buses Modules Systems Chips Miscellany
Mike Spooner, revised 28th December 2000