The initial expectations at Sun were that 50MHz MBus implementations were achievable with conventional design and manufacturing techniques, with an implication that higher speeds may be achievable later.
Sun's initial MBus implementation ran at 40MHz, using a PGA-packaged error-correcting memory-controller (known as the EMC).
Sun did not produce a 50MHz MBus until 1994, which used a much smaller surface-mount-packaged "system memory-controller" (known as the SMC). This was the highest MBus clock-speed released by Sun.
Most Sun clones (with the notable exceptions of several Axil/Hyundai systems and the Ross HyperSTATION and SPARCplug) used one of the Sun EMC or SMC memory-controller chips. Although the (50MHz) SMC chip was also available as a PGA-packaged part, I am not aware of any retail system that used the PGA version at 50MHz (it was used in the rare SPARCstation-10SX, but only at 40MHz).
Cray's system-boards for the CS6400 server had a 55MHz XBus, probably designed with considerable help from Sun, and possibly using a custom memory-controller.
Ross Technology designed their own MBus memory-controller (the RT521) for their HyperSTATION and SPARCplug systems, that had a programmable MBus clock-generator supporting 50, 60, 66 and 75MHz. However, 75MHz could only be made to work with in prototype systems with a directly soldered HyperSPARC CPU (not a module), and even then only if you were very lucky - 70MHz was the practical limit. Initially, even 60 and 66MHz would only work in the single-slot SPARCplug, not in the dual-slot HyperSTATION.
Ross later produced a specially packaged BGA variant of the RT521 that enabled reliable 60 and 66MHz MBus operation for the later HyperSTATION-30 motherboards.
Even then, the CPU modules had to be soak-tested in dual-module configurations on the 66MHz MBus - some modules were qualified only for use in 40/50MHz MBus configurations. Note that only RT626-based MBus modules (excluding HM180S-512, HMx4S-512, HMx4D-512 and HMx4.5S-512) were designed for operation on 60/66MHz MBus, and would still only work above 50MHz if the host MBus implementation was up to it.
As already noted, the MBus specifications themselves made high-speed bus clock a tricky proposition. The properties of the MBus slot-connector are probably the limiting factor, followed by the total conductor/trace lengths and tolerances and by the capacitance/impedance characteristics.
A pity, as a faster MBus makes a big difference in performance.
|Mike Spooner, revised 17th July 2000|