The Rough Guide to MBus Modules
Introduction Buses Modules Systems Chips Miscellany


SuperSPARC Chips


SuperSPARC Microprocessors

Sun Microelectronics
Product Name
Type Rev. Max. Clock
(MHz)
Initial Revision
Release Date
stp1020n SuperSPARC-I 1.2 40 1990
2.2, 2.4 mostly 40, some certified at 45 1990
stp1020 SuperSPARC-I 3.1, 3.2, 3.3, 3.5 50 1991
stp1020a SuperSPARC-I 5.0, 5.1, 5.2 60 1991
stp1021 SuperSPARC-II 1.6 75 1994
stp1021a SuperSPARC-II 2.3, 2.4, 2.4.3, 2.4.5 90 1994

SM81 and SM81-2 modules use STP1021A chips at 85MHz, deliberately clocked below the rated maximum of 90MHz to reduce heat dissipation that could otherwise harm adjacent components in some systems. Chip-yield may have been slightly better at 85MHz, too.

The SuperSPARC-I has a "bus-type-selector" input signal, to select the behaviour of the bus: either MBus or VBus. Thus it can be used to construct cacheless modules, as well as cached ones.

The SuperSPARC-II bus behaviour is always VBus, thus it cannot be used to construct cacheless modules.


SuperCache Controllers (aka MXCC aka MCC)

Sun Microelectronics
Product Name
Type Rev. Max.
VBus Clock
(MHz)
Max.
MBus/XBus Clock
(MHz)
Initial Revision
Release Date
stp1090 MXCC 1.x 40, 45? 40 1991
stp1090a MXCC 2.x 50 50 1991
3.x, 3.1, 3.3 75
stp1091 MXCC 4.4, 4.5 90 50 (maybe 55?) 1994

The STP1091 (MXCC rev 4.x) has a "multiple-commands mode" which allows concurrently-outstanding memory-references from the SuperSPARC CPU to be concurrently-outstanding beyond the level 2 cache, all the way onto the MBus/XBus.

Earlier MXCC chips did not have this performance-enhancement: concurrently-outstanding memory-references from the SuperSPARC CPU would be serialised out onto the MBus/XBus in the event of a cache miss.

Note: even SuperSPARC-I CPUs had "multiple-commands mode".


Introduction Buses Modules Systems Chips Miscellany
Mike Spooner, revised 6th December 2000