All MBus-based computers use SPARC-architecture CPUs. Usually, the CPUs are mounted on plug-in daughter-cards, called "modules". Most MBus systems provide one or more "slots" into which modules can be plugged: each module contains one or two CPUs and (optionally) some second-level cache memory.
In principle, the MBus can support a maximum of 8 "nodes", one of which must be a memory-controller (a "North Bridge" in PC terms), another was typically an I/O-bus interface (a "South Bridge"), thus leaving a capacity for upto 6 CPUs. However, none of the MBus implementations actually produced could support more than 4 CPUs, although a few systems accomodated more CPUs by having several independant MBuses.
CPU modules lacking a L2 cache-controller take their CPU clock directly from the MBus clock.
The HMx4.5S, HMx4S and HMx4D CPU modules generate their CPU clock by multiplying the MBus clock. For instance, the HMx4S runs at 160MHz on a 40MHz MBus, but at 200MHz on a 50MHz MBus.
The other CPU modules generate their own CPU clock internally (using a phase-locked-loop circuit), which must be at least equal-to (for HyperSPARC-based modules) or faster than (for SuperSPARC modules) than the MBus clock.
For example: SM41 will run on a 40MHz MBus (because it is actually internally clocked at 40.3MHz); SM40, SM41 and SM51 will not run on a 50MHz MBus; whereas SM50 would run at 50MHz on a 50MHz MBus, or at 40Mhz on a 40MHz MBus.
Some system chipsets that are normally clocked at 50MHz, are capable of automatically reducing their MBus speed to 40MHz in the presence of SM40, SM41, SM52 or SM51 modules.
This leads to the strange situation that in the SPARCstation-20, uncached SM50 modules can outperform cached SM51 modules for some workloads (because they allow the SS20 MBus to run at full speed).
See also: Whither the High-Speed MBus?.
These systems have multiple system-boards, each with CPU-, memory- and I/O-slots. The system-boards are connected together via one or more XDBus backplanes. All memory is "owned" by an XDBus, rather than an XBus, even "local" memory.
The XBus uses the same slot-connectors as the MBus, and some MBus CPU modules are also XBus modules - they automatically detect the host bus protocol and adapt accordingly. Thus, IMHO, it is appropriate to include XBus systems in this guide.
I am not sure whether the XBus protocol would prevent use of dual-CPU modules or not. If you know, please email email@example.com.
The XBus can only use modules that contain a Sun MXCC L2 cache-controller (cached SuperSPARC modules).
The XBus runs at a fixed clock-speed, regardless of the CPU modules installed. Unlike MBus, such modules can run at the same or a higher clock-speed than the XBus itself.
For example: SM100, SM40 and HyperSPARC modules cannot be used (no MXCC); SM41 modules can be used on a 40MHz XBus but not a 50MHz one; SM51 modules will run at 50MHz on both a 40MHz or 50MHz XBus.
KBus does not in itself effect the module-configuration of those MBuses.
Note that the SuperSPARC-I CPU chip could run on an MBus or VBus, selected via an input control pin.
The other manufacturer of MBus modules with an L2 cache, Ross Technologies (now Bridgepoint), used their own private intra-module bus between CPU and cache-controller.
These buses do not directly effect the module-configuration of the MBus, at least as far as we are concerned here.
|Mike Spooner, revised 9th May 2006|